initrd_filename, 0, NULL);
}
+/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
+ BIOS will read it and start S3 resume at POST Entry*/
+void cmos_set_s3_resume(void)
+{
+ if (rtc_state)
+ rtc_set_memory(rtc_state, 0xF, 0xFE);
+}
+
QEMUMachine pc_machine = {
"pc",
"Standard PC",
#include "vl.h"
#include <xen/hvm/ioreq.h>
+#include <xen/hvm/params.h>
/* PM1a_CNT bits, as defined in the ACPI specification. */
#define SCI_EN (1 << 0)
/* Sleep state type codes as defined by the \_Sx objects in the DSDT. */
/* These must be kept in sync with the DSDT (hvmloader/acpi/dsdt.asl) */
#define SLP_TYP_S4 (6 << 10)
+#define SLP_TYP_S3 (5 << 10)
#define SLP_TYP_S5 (7 << 10)
#define ACPI_DBG_IO_ADDR 0xb044
PHPSlots php_slots;
+int s3_shutdown_flag;
+
static void piix4acpi_save(QEMUFile *f, void *opaque)
{
PCIAcpiState *s = opaque;
return;
switch (val & SLP_TYP_Sx) {
+ case SLP_TYP_S3:
+ s3_shutdown_flag = 1;
+ qemu_system_reset();
+ s3_shutdown_flag = 0;
+ cmos_set_s3_resume();
+ xc_set_hvm_param(xc_handle, domid, HVM_PARAM_ACPI_S_STATE, 3);
+ break;
case SLP_TYP_S4:
case SLP_TYP_S5:
qemu_system_shutdown_request();
/* called from main_cpu_reset */
void cpu_reset(CPUX86State *env)
{
+ extern int s3_shutdown_flag;
int xcHandle;
int sts;
+
+ if (s3_shutdown_flag)
+ return;
xcHandle = xc_interface_open();
if (xcHandle < 0)
void ioport_set_a20(int enable);
int ioport_get_a20(void);
+void cmos_set_s3_resume(void);
/* ppc.c */
extern QEMUMachine prep_machine;