nested vmx: emulate IA32_VMX_MISC MSR
authorDongxiao Xu <dongxiao.xu@intel.com>
Tue, 8 Jan 2013 09:42:19 +0000 (10:42 +0100)
committerDongxiao Xu <dongxiao.xu@intel.com>
Tue, 8 Jan 2013 09:42:19 +0000 (10:42 +0100)
Use the host value to emulate IA32_VMX_MISC MSR for L1 VMM.
For CR3-target value, we don't support this feature currently and
set the number to zero.

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/hvm/vmx/vvmx.c
xen/include/asm-x86/hvm/vmx/vmcs.h

index 7b27d2ddc7c9d79c0fb3eaebbaea18add651c9e0..16fb3fd1ae846e6057bfd927e8251983e4536946 100644 (file)
@@ -1462,7 +1462,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         data = 0x267ff & ~X86_CR4_SMXE;
         break;
     case MSR_IA32_VMX_MISC:
-        gdprintk(XENLOG_WARNING, "VMX MSR %x not fully supported yet.\n", msr);
+        /* Do not support CR3-target feature now */
+        data = host_data & ~VMX_MISC_CR3_TARGET;
         break;
     default:
         r = 0;
index ef2c9c993bb832c96af79c78e44e9cd5f389ddd0..3adffccac838e52c3ed1ef824e1b12ab71ee8d2c 100644 (file)
@@ -209,6 +209,8 @@ extern bool_t cpu_has_vmx_ins_outs_instr_info;
 #define VMX_VPID_INVVPID_ALL_CONTEXT                        0x40000000000ULL
 #define VMX_VPID_INVVPID_SINGLE_CONTEXT_RETAINING_GLOBAL    0x80000000000ULL
 
+#define VMX_MISC_CR3_TARGET             0x1ff0000
+
 #define cpu_has_wbinvd_exiting \
     (vmx_secondary_exec_control & SECONDARY_EXEC_WBINVD_EXITING)
 #define cpu_has_vmx_virtualize_apic_accesses \