[XEN] Fix 64-bit build.

This required fiddling the asm constraints of the atomic bitops. It
seems gcc isn't entirely happy with "+m": the manual says that the
'+' modifier should be used only when a register constraint is
available.

Signed-off-by: Keir Fraser <keir@xensource.com>

diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index 098b61474ca8a998812a0e2db1bad0eca9b6bdc8..f0a3f88cee0d54978fd54388e587198a5aea9984 100644 (file)
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -399,7 +399,8 @@ static void ioapic_deliver(struct vioapic *vioapic, int irq)
     struct vlapic *target;
 
     HVM_DBG_LOG(DBG_LEVEL_IOAPIC,
-                "dest %x dest_mode %x delivery_mode %x vector %x trig_mode %x\n",
+                "dest=%x dest_mode=%x delivery_mode=%x "
+                "vector=%x trig_mode=%x\n",
                 dest, dest_mode, delivery_mode, vector, trig_mode);
 
     deliver_bitmask = ioapic_get_delivery_bitmask(
@@ -430,8 +431,8 @@ static void ioapic_deliver(struct vioapic *vioapic, int irq)
         }
         else
         {
-            HVM_DBG_LOG(DBG_LEVEL_IOAPIC,
-                        "null round robin mask %x vector %x delivery_mode %x\n",
+            HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "null round robin: "
+                        "mask=%x vector=%x delivery_mode=%x\n",
                         deliver_bitmask, vector, dest_LowestPrio);
         }
         break;

diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 4f679e60aca8953d292a7ec520cd62a404ae5794..8882784a7f2fdffcce905851c27f85ef4e0ca161 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -420,7 +420,7 @@ static int construct_vmcs(struct vcpu *v)
     error |= __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
                        v->arch.hvm_vcpu.u.vmx.exec_control);
     error |= __vmwrite(VIRTUAL_APIC_PAGE_ADDR,
-                       page_to_maddr(v->arch.hvm_vcpu.vlapic->regs_page));
+                       page_to_maddr(vcpu_vlapic(v)->regs_page));
     error |= __vmwrite(TPR_THRESHOLD, 0);
 #endif
 

diff --git a/xen/include/asm-x86/bitops.h b/xen/include/asm-x86/bitops.h
index 14d7e1451b3b128b82c555dc58bc04b1dcfb769c..4c954663eb2f6cd58f4e18867273dadb7d018d4f 100644 (file)
--- a/xen/include/asm-x86/bitops.h
+++ b/xen/include/asm-x86/bitops.h
@@ -14,10 +14,12 @@
 #endif
 
 /*
- * We use the "+m" constraint because the memory operand is both read from
- * and written to. Since the operand is in fact a word array, we also
- * specify "memory" in the clobbers list to indicate that words other than
- * the one directly addressed by the memory operand may be modified.
+ * We specify the memory operand as both input and output because the memory
+ * operand is both read from and written to. Since the operand is in fact a
+ * word array, we also specify "memory" in the clobbers list to indicate that
+ * words other than the one directly addressed by the memory operand may be
+ * modified. We don't use "+m" because the gcc manual says that it should be
+ * used only when the constraint allows the operand to reside in a register.
  */
 
 #define ADDR (*(volatile long *) addr)
@@ -36,8 +38,8 @@ static __inline__ void set_bit(int nr, volatile void * addr)
 {
        __asm__ __volatile__( LOCK_PREFIX
                "btsl %1,%0"
-               :"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
 }
 
 /**
@@ -53,8 +55,8 @@ static __inline__ void __set_bit(int nr, volatile void * addr)
 {
        __asm__(
                "btsl %1,%0"
-               :"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
 }
 
 /**
@@ -71,8 +73,8 @@ static __inline__ void clear_bit(int nr, volatile void * addr)
 {
        __asm__ __volatile__( LOCK_PREFIX
                "btrl %1,%0"
-               :"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
 }
 
 /**
@@ -88,8 +90,8 @@ static __inline__ void __clear_bit(int nr, volatile void * addr)
 {
        __asm__(
                "btrl %1,%0"
-               :"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
 }
 
 #define smp_mb__before_clear_bit()     barrier()
@@ -108,8 +110,8 @@ static __inline__ void __change_bit(int nr, volatile void * addr)
 {
        __asm__ __volatile__(
                "btcl %1,%0"
-               :"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
 }
 
 /**
@@ -125,8 +127,8 @@ static __inline__ void change_bit(int nr, volatile void * addr)
 {
        __asm__ __volatile__( LOCK_PREFIX
                "btcl %1,%0"
-               :"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
 }
 
 /**
@@ -143,8 +145,8 @@ static __inline__ int test_and_set_bit(int nr, volatile void * addr)
 
        __asm__ __volatile__( LOCK_PREFIX
                "btsl %2,%1\n\tsbbl %0,%0"
-               :"=r" (oldbit),"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=r" (oldbit),"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
        return oldbit;
 }
 
@@ -163,8 +165,8 @@ static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
 
        __asm__(
                "btsl %2,%1\n\tsbbl %0,%0"
-               :"=r" (oldbit),"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=r" (oldbit),"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
        return oldbit;
 }
 
@@ -182,8 +184,8 @@ static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
 
        __asm__ __volatile__( LOCK_PREFIX
                "btrl %2,%1\n\tsbbl %0,%0"
-               :"=r" (oldbit),"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=r" (oldbit),"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
        return oldbit;
 }
 
@@ -202,8 +204,8 @@ static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
 
        __asm__(
                "btrl %2,%1\n\tsbbl %0,%0"
-               :"=r" (oldbit),"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=r" (oldbit),"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
        return oldbit;
 }
 
@@ -214,8 +216,8 @@ static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
 
        __asm__ __volatile__(
                "btcl %2,%1\n\tsbbl %0,%0"
-               :"=r" (oldbit),"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=r" (oldbit),"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
        return oldbit;
 }
 
@@ -233,8 +235,8 @@ static __inline__ int test_and_change_bit(int nr, volatile void * addr)
 
        __asm__ __volatile__( LOCK_PREFIX
                "btcl %2,%1\n\tsbbl %0,%0"
-               :"=r" (oldbit),"+m" (ADDR)
-               :"dIr" (nr) : "memory");
+               :"=r" (oldbit),"=m" (ADDR)
+               :"dIr" (nr), "m" (ADDR) : "memory");
        return oldbit;
 }