arm64: ITS: fix cacheability adjustment

If the host GICv3 redistributor reports that the pending table cannot
use shareable memory, we try to drop the cacheability attributes as
well. However we fail horribly in doing computer science 101 bit
masking, effectively clearing the whole register instead of just a few
bits.
Fix this by removing the one redundant masking operation and adding the
magic negation for the actually needed other operation.

Reported-by: Manish Jaggi <manish.jaggi@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Reviewed-by: Julien Grall <julien.grall@linaro.org>
Release-Acked-by: Julien Grall <julien.grall@linaro.org>

diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
index c3474f5434b69b1f71fdd8516c2254f4d750ab1a..84582157b8bac77c2c5e33bd3145e62a61f37783 100644 (file)
--- a/xen/arch/arm/gic-v3-lpi.c
+++ b/xen/arch/arm/gic-v3-lpi.c
@@ -359,8 +359,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base)
     /* If the hardware reports non-shareable, drop cacheability as well. */
     if ( !(table_reg & GICR_PENDBASER_SHAREABILITY_MASK) )
     {
-        table_reg &= GICR_PENDBASER_SHAREABILITY_MASK;
-        table_reg &= GICR_PENDBASER_INNER_CACHEABILITY_MASK;
+        table_reg &= ~GICR_PENDBASER_INNER_CACHEABILITY_MASK;
         table_reg |= GIC_BASER_CACHE_nC << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT;
 
         writeq_relaxed(table_reg, rdist_base + GICR_PENDBASER);