drivers/char: pl011: Enable receive timeout interrupt

The commit 874f76a "PL011: fix reverse logic for interrupt mask register"
introduced regression on the Versatile Express. The board didn't receive
correctly input.

The timeout interrupt may be asserted when the FIFO is not empty, and no futher
data is received over a 32-bit period.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 0e1eb64601f5bb169617e3a72eb4154a4916e2ab..e4bd702f3fefb0fd2cb8a3913d1ddeaf49a219ca 100644 (file)
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -140,7 +140,7 @@ static void __init pl011_init_postirq(struct serial_port *port)
     pl011_write(uart, ICR, OEI|BEI|PEI|FEI);
 
     /* Unmask interrupts */
-    pl011_write(uart, IMSC, OEI|BEI|PEI|FEI|TXI|RXI);
+    pl011_write(uart, IMSC, RTI|OEI|BEI|PEI|FEI|TXI|RXI);
 }
 
 static void pl011_suspend(struct serial_port *port)