ASSERT(intack.source != hvm_intsrc_none);
- HVMTRACE_2D(INJ_VIRQ, 0x0, /*fake=*/ 1);
+ HVMTRACE_3D(INTR_WINDOW, intack.vector, intack.source,
+ vmcb->eventinj.fields.v?vmcb->eventinj.fields.vector:-1);
/*
* Create a dummy virtual interrupt to intercept as soon as the
ASSERT(intack.source != hvm_intsrc_none);
+ if ( unlikely(tb_init_done) )
+ {
+ unsigned int intr = __vmread(VM_ENTRY_INTR_INFO);
+ HVMTRACE_3D(INTR_WINDOW, intack.vector, intack.source,
+ (intr & INTR_INFO_VALID_MASK) ? intr & 0xff : -1);
+ }
+
if ( (intack.source == hvm_intsrc_nmi) && cpu_has_vmx_vnmi )
{
/*
#define DO_TRC_HVM_INJ_EXC DEFAULT_HVM_INJECT
#define DO_TRC_HVM_INJ_VIRQ DEFAULT_HVM_INJECT
#define DO_TRC_HVM_REINJ_VIRQ DEFAULT_HVM_INJECT
+#define DO_TRC_HVM_INTR_WINDOW DEFAULT_HVM_INJECT
#define DO_TRC_HVM_IO_READ DEFAULT_HVM_IO
#define DO_TRC_HVM_IO_WRITE DEFAULT_HVM_IO
#define DO_TRC_HVM_CR_READ DEFAULT_HVM_REGACCESS
#define TRC_HVM_CLTS (TRC_HVM_HANDLER + 0x18)
#define TRC_HVM_LMSW (TRC_HVM_HANDLER + 0x19)
#define TRC_HVM_LMSW64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19)
+#define TRC_HVM_INTR_WINDOW (TRC_HVM_HANDLER + 0X20)
/* trace subclasses for power management */
#define TRC_PM_FREQ 0x00801000 /* xen cpu freq events */