IA64: Rationalize VMM mode alignment checking

This is the xen port of ia64 linux chageset of
b704882e70d87d7f56db5ff17e2253f3fa90e4f3

    [IA64] Rationalize kernel mode alignment checking

    Itanium processors can handle some misaligned data accesses. They
    also provide a mode where all such accesses are forced to trap. The
    kernel was schizophrenic about use of this mode:

    * Base kernel code ran in permissive mode where the only traps
      generated were from those cases that the h/w could not handle.
    * Interrupt, syscall and trap code ran in strict mode where all
      unaligned accesses caused traps to the 0x5a00 unaligned reference
      vector.

    Use strict alignment checking throughout the kernel, but make
    sure that we continue to let user mode use more relaxed mode
    as the default.

    Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

diff --git a/xen/arch/ia64/linux-xen/head.S b/xen/arch/ia64/linux-xen/head.S
index 0c997f593a1a86ec8ef2ea72e1445fcb3c7d4076..2ef757b46d8414310292e4b92ae809cc9dbae236 100644 (file)
--- a/xen/arch/ia64/linux-xen/head.S
+++ b/xen/arch/ia64/linux-xen/head.S
@@ -267,8 +267,13 @@ start_ap:
        /*
         * Switch into virtual mode:
         */
+#ifdef XEN
+               movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
+                 |IA64_PSR_DI|IA64_PSR_AC)
+#else
        movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
                  |IA64_PSR_DI)
+#endif
        ;;
        mov cr.ipsr=r16
        movl r17=1f