int i, j;
j = 1 << (PAGE_SHIFT-PAGE_SHIFT_4K);
for(i = 0 ; i < j; i++)
- iommu_map_page(d, gpfn*j + i, mfn*j + i);
+ iommu_map_page(d, gpfn*j + i, mfn*j + i,
+ IOMMUF_readable|IOMMUF_writable);
}
}
iommu_unmap_page(d, mfn_to_gmfn(d, page_to_mfn(page)));
else if ( type == PGT_writable_page )
iommu_map_page(d, mfn_to_gmfn(d, page_to_mfn(page)),
- page_to_mfn(page));
+ page_to_mfn(page),
+ IOMMUF_readable|IOMMUF_writable);
}
}
if ( order == EPT_TABLE_ORDER )
{
for ( i = 0; i < (1 << order); i++ )
- iommu_map_page(d, gfn - offset + i, mfn_x(mfn) - offset + i);
+ iommu_map_page(
+ d, gfn - offset + i, mfn_x(mfn) - offset + i,
+ IOMMUF_readable|IOMMUF_writable);
}
else if ( !order )
- iommu_map_page(d, gfn, mfn_x(mfn));
+ iommu_map_page(
+ d, gfn, mfn_x(mfn), IOMMUF_readable|IOMMUF_writable);
}
else
{
{
if ( p2mt == p2m_ram_rw )
for ( i = 0; i < (1UL << page_order); i++ )
- iommu_map_page(d, gfn+i, mfn_x(mfn)+i );
+ iommu_map_page(d, gfn+i, mfn_x(mfn)+i,
+ IOMMUF_readable|IOMMUF_writable);
else
for ( int i = 0; i < (1UL << page_order); i++ )
iommu_unmap_page(d, gfn+i);
if ( need_iommu(d) && t == p2m_ram_rw )
{
for ( i = 0; i < (1 << page_order); i++ )
- if ( (rc = iommu_map_page(d, mfn + i, mfn + i)) != 0 )
+ {
+ rc = iommu_map_page(
+ d, mfn + i, mfn + i, IOMMUF_readable|IOMMUF_writable);
+ if ( rc != 0 )
{
while ( i-- > 0 )
iommu_unmap_page(d, mfn + i);
return rc;
}
+ }
}
return 0;
}
goto destroy_m2p;
for ( i = spfn; i < epfn; i++ )
- if ( iommu_map_page(dom0, i, i) )
+ if ( iommu_map_page(dom0, i, i, IOMMUF_readable|IOMMUF_writable) )
break;
if ( i != epfn )
BUG_ON(paging_mode_translate(ld));
/* We're not translated, so we know that gmfns and mfns are
the same things, so the IOMMU entry is always 1-to-1. */
- if ( iommu_map_page(ld, frame, frame) )
+ if ( iommu_map_page(ld, frame, frame,
+ IOMMUF_readable|IOMMUF_writable) )
{
rc = GNTST_general_error;
goto undo_out;
return next_table_maddr;
}
-int amd_iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn)
+int amd_iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn,
+ unsigned int flags)
{
u64 iommu_l2e;
struct hvm_iommu *hd = domain_hvm_iommu(d);
- int iw = IOMMU_IO_WRITE_ENABLED;
- int ir = IOMMU_IO_READ_ENABLED;
BUG_ON( !hd->root_table );
domain_crash(d);
return -EFAULT;
}
- set_iommu_l1e_present(iommu_l2e, gfn, (u64)mfn << PAGE_SHIFT, iw, ir);
+
+ set_iommu_l1e_present(iommu_l2e, gfn, (u64)mfn << PAGE_SHIFT,
+ !!(flags & IOMMUF_writable),
+ !!(flags & IOMMUF_readable));
spin_unlock(&hd->mapping_lock);
return 0;
{
/* setup 1:1 page table for dom0 */
for ( i = 0; i < max_page; i++ )
- amd_iommu_map_page(domain, i, i);
+ amd_iommu_map_page(domain, i, i,
+ IOMMUF_readable|IOMMUF_writable);
}
amd_iommu_setup_dom0_devices(domain);
{
BUG_ON(SHARED_M2P(mfn_to_gmfn(d, page_to_mfn(page))));
rc = hd->platform_ops->map_page(
- d, mfn_to_gmfn(d, page_to_mfn(page)), page_to_mfn(page));
+ d, mfn_to_gmfn(d, page_to_mfn(page)), page_to_mfn(page),
+ IOMMUF_readable|IOMMUF_writable);
if (rc)
{
spin_unlock(&d->page_alloc_lock);
}
}
-int iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn)
+int iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn,
+ unsigned int flags)
{
struct hvm_iommu *hd = domain_hvm_iommu(d);
if ( !iommu_enabled || !hd->platform_ops )
return 0;
- return hd->platform_ops->map_page(d, gfn, mfn);
+ return hd->platform_ops->map_page(d, gfn, mfn, flags);
}
int iommu_unmap_page(struct domain *d, unsigned long gfn)
pfn = page_addr >> PAGE_SHIFT;
tmp = 1 << (PAGE_SHIFT - PAGE_SHIFT_4K);
for ( j = 0; j < tmp; j++ )
- iommu_map_page(d, (pfn*tmp+j), (pfn*tmp+j));
+ iommu_map_page(d, (pfn*tmp+j), (pfn*tmp+j),
+ IOMMUF_readable|IOMMUF_writable);
page_addr += PAGE_SIZE;
}
static int intel_iommu_map_page(
- struct domain *d, unsigned long gfn, unsigned long mfn)
+ struct domain *d, unsigned long gfn, unsigned long mfn,
+ unsigned int flags)
{
struct hvm_iommu *hd = domain_hvm_iommu(d);
struct acpi_drhd_unit *drhd;
pte = page + (gfn & LEVEL_MASK);
pte_present = dma_pte_present(*pte);
dma_set_pte_addr(*pte, (paddr_t)mfn << PAGE_SHIFT_4K);
- dma_set_pte_prot(*pte, DMA_PTE_READ | DMA_PTE_WRITE);
+ dma_set_pte_prot(*pte,
+ ((flags & IOMMUF_readable) ? DMA_PTE_READ : 0) |
+ ((flags & IOMMUF_writable) ? DMA_PTE_WRITE : 0));
/* Set the SNP on leaf page table if Snoop Control available */
if ( iommu_snoop )
while ( base_pfn < end_pfn )
{
- if ( intel_iommu_map_page(d, base_pfn, base_pfn) )
+ if ( intel_iommu_map_page(d, base_pfn, base_pfn,
+ IOMMUF_readable|IOMMUF_writable) )
return -1;
base_pfn++;
}
tmp = 1 << (PAGE_SHIFT - PAGE_SHIFT_4K);
for ( j = 0; j < tmp; j++ )
- iommu_map_page(d, (i*tmp+j), (i*tmp+j));
+ iommu_map_page(d, (i*tmp+j), (i*tmp+j),
+ IOMMUF_readable|IOMMUF_writable);
if (!(i & (0xfffff >> (PAGE_SHIFT - PAGE_SHIFT_4K))))
process_pending_softirqs();
#define MAX_AMD_IOMMUS 32
#define IOMMU_PAGE_TABLE_LEVEL_3 3
#define IOMMU_PAGE_TABLE_LEVEL_4 4
-#define IOMMU_IO_WRITE_ENABLED 1
-#define IOMMU_IO_READ_ENABLED 1
-#define HACK_BIOS_SETTINGS 0
/* interrupt remapping table */
#define INT_REMAP_INDEX_DM_MASK 0x1C00
int __init amd_iommu_update_ivrs_mapping_acpi(void);
/* mapping functions */
-int amd_iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn);
+int amd_iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn,
+ unsigned int flags);
int amd_iommu_unmap_page(struct domain *d, unsigned long gfn);
u64 amd_iommu_get_next_table_from_pte(u32 *entry);
int amd_iommu_reserve_domain_unity_map(struct domain *domain,
int deassign_device(struct domain *d, u8 bus, u8 devfn);
int iommu_get_device_group(struct domain *d, u8 bus, u8 devfn,
XEN_GUEST_HANDLE_64(uint32) buf, int max_sdevs);
-int iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn);
+
+/* iommu_map_page() takes flags to direct the mapping operation. */
+#define _IOMMUF_readable 0
+#define IOMMUF_readable (1u<<_IOMMUF_readable)
+#define _IOMMUF_writable 1
+#define IOMMUF_writable (1u<<_IOMMUF_writable)
+int iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn,
+ unsigned int flags);
int iommu_unmap_page(struct domain *d, unsigned long gfn);
+
void iommu_domain_teardown(struct domain *d);
int hvm_do_IRQ_dpci(struct domain *d, unsigned int irq);
int dpci_ioport_intercept(ioreq_t *p);
int (*remove_device)(struct pci_dev *pdev);
int (*assign_device)(struct domain *d, u8 bus, u8 devfn);
void (*teardown)(struct domain *d);
- int (*map_page)(struct domain *d, unsigned long gfn, unsigned long mfn);
+ int (*map_page)(struct domain *d, unsigned long gfn, unsigned long mfn,
+ unsigned int flags);
int (*unmap_page)(struct domain *d, unsigned long gfn);
int (*reassign_device)(struct domain *s, struct domain *t,
u8 bus, u8 devfn);