x86/levelling: fix breakage on older Intel boxes from c/s 08e7738

cpufeat_mask() yields an unsigned integer constant.  As a result, taking its
complement causes zero extention rather than sign extention.

The result is that, when a guest OS has OXSAVE disabled, all features in 1d
are hidden from native CPUID.  Amongst other things, this causes the early
code in Linux to find no LAPIC, but for everything to appear fine later when
userspace is up and running.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Tested-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index a9355cbfa1cdf96c5d2ded7569708fb31ad75b79..7b60aaa6fce63713a5aa28b67176e48f1dbb8234 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -192,7 +192,7 @@ static void intel_ctxt_switch_levelling(const struct vcpu *next)
                 */
                if (next && is_pv_vcpu(next) && !is_idle_vcpu(next) &&
                    !(next->arch.pv_vcpu.ctrlreg[4] & X86_CR4_OSXSAVE))
-                       val &= ~cpufeat_mask(X86_FEATURE_OSXSAVE);
+                       val &= ~(uint64_t)cpufeat_mask(X86_FEATURE_OSXSAVE);
 
                if (unlikely(these_masks->_1cd != val)) {
                        wrmsrl(msr_basic, val);