static int check_cx(struct acpi_processor_power *power, xen_processor_cx_t *cx)
{
static int bm_check_flag;
- if ( cx == NULL )
- return -EINVAL;
switch ( cx->reg.space_id )
{
/* assume all logical cpu has the same support for mwait */
if ( acpi_processor_ffh_cstate_probe(cx) )
- return -EFAULT;
+ return -EINVAL;
}
break;
if ( cx->type == ACPI_STATE_C3 )
{
+ /* We must be able to use HPET in place of LAPIC timers. */
+ if ( !hpet_broadcast_is_available() )
+ return -EINVAL;
+
/* All the logic here assumes flags.bm_check is same across all CPUs */
if ( !bm_check_flag )
{
/* bus mastering control is necessary */
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"C3 support requires BM control\n"));
- return -1;
+ return -EINVAL;
}
else
{
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"Cache invalidation should work properly"
" for C3 to be enabled on SMP systems\n"));
- return -1;
+ return -EINVAL;
}
acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
}
return 0;
}
-static int set_cx(struct acpi_processor_power *acpi_power,
- xen_processor_cx_t *xen_cx)
+static void set_cx(
+ struct acpi_processor_power *acpi_power,
+ xen_processor_cx_t *xen_cx)
{
struct acpi_processor_cx *cx;
- /* skip unsupported acpi cstate */
- if ( check_cx(acpi_power, xen_cx) )
- return -EFAULT;
+ if ( check_cx(acpi_power, xen_cx) != 0 )
+ return;
cx = &acpi_power->states[xen_cx->type];
if ( !cx->valid )
cx->power = xen_cx->power;
cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
-
- return 0;
}
int get_cpu_id(u8 acpi_id)
reprogram_timer(per_cpu(timer_deadline, cpu));
}
+int hpet_broadcast_is_available(void)
+{
+ return (hpet_event.event_handler == handle_hpet_broadcast);
+}
+
int hpet_legacy_irq_tick(void)
{
if ( !hpet_event.event_handler )