xen/arm: Implement MPIDR per VCPU

Use different affinity for each VCPU and always expose an SMP systems to
the guest.

Signed-off-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
[ ijc -- s/AFFO/AFF0/ in a comment ]

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 6937abf6af60b81e069f25e4bf098a31643abde2..373c7b37a32607433f57882846eb6dfe4eb57efe 100644 (file)
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -140,7 +140,7 @@ static void ctxt_switch_to(struct vcpu *n)
     isb();
 
     WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2);
-    WRITE_SYSREG(n->domain->arch.vmpidr, VMPIDR_EL2);
+    WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2);
 
     /* VGIC */
     gic_restore_state(n);
@@ -451,7 +451,14 @@ int vcpu_initialise(struct vcpu *v)
         return rc;
 
     v->arch.sctlr = SCTLR_BASE;
+    /*
+     * By default exposes an SMP system with AFF0 set to the VCPU ID
+     * TODO: Handle multi-threading processor and cluster
+     */
+    v->arch.vmpidr = MPIDR_SMP | (v->vcpu_id << MPIDR_AFF0_SHIFT);
+
     v->arch.actlr = READ_SYSREG32(ACTLR_EL1);
+
     /* XXX: Handle other than CA15 cpus */
     if ( v->domain->max_vcpus > 1 )
         v->arch.actlr |= ACTLR_CA15_SMP;
@@ -490,7 +497,6 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags)
 
     /* Default the virtual ID to match the physical */
     d->arch.vpidr = boot_cpu_data.midr.bits;
-    d->arch.vmpidr = boot_cpu_data.mpidr.bits;
 
     clear_page(d->shared_info);
     share_xen_page_with_guest(

diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 339b6e69ad4a4f58fa1f45501776e31bc9d7cb20..104928212306307a9a741bc0730cba4914cd8933 100644 (file)
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -68,7 +68,6 @@ struct arch_domain
 
     /* Virtual CPUID */
     uint32_t vpidr;
-    register_t vmpidr;
 
     struct {
         uint64_t offset;
@@ -194,6 +193,7 @@ struct arch_vcpu
 
     /* CP 15 */
     uint32_t csselr;
+    register_t vmpidr;
 
     uint32_t gic_hcr, gic_vmcr, gic_apr;
     uint32_t gic_lr[64];

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 263bd0328d2f6bf105c74346d36c81c421be58a4..5181e7bd8964644004a2637143df7fab9d20219a 100644 (file)
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -3,6 +3,15 @@
 
 #include <asm/cpregs.h>
 
+/* MIDR Main ID Register */
+#define MIDR_MASK    0xff0ffff0
+
+/* MPIDR Multiprocessor Affinity Register */
+#define MPIDR_UP            (1 << 30)
+#define MPIDR_SMP           (1 << 31)
+#define MPIDR_AFF0_SHIFT    (0)
+#define MPIDR_AFF0_MASK     (0xff << MPIDR_AFF0_SHIFT)
+
 /* TTBCR Translation Table Base Control Register */
 #define TTBCR_EAE    0x80000000
 #define TTBCR_N_MASK 0x07