x86/amd: protect set_cpuidmask() against #GP faults

Virtual environments such as Xen HVM containers and VirtualBox do not
necessarily provide support for feature masking MSRs.

As their presence is detected by model numbers alone, and their use predicated
on command line parameters, use the safe() variants of {wr,rd}msr() to avoid
dying with an early #GP fault.

In fact, use the password variants in all cases because:
    a) they are safe to use even if not strictly required
    b) have a more useful function prototype for this purposes

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index ea158cb48ce87f60b4614c098d1ee419f998c1be..ba6b63e7cbcdb6d677eacde24466731345ca6717 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -151,6 +151,7 @@ static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
        static unsigned int extfeat_ecx, extfeat_edx;
        static unsigned int l7s0_eax, l7s0_ebx;
        static unsigned int thermal_ecx;
+       static bool_t skip_feat, skip_extfeat;
        static bool_t skip_l7s0_eax_ebx, skip_thermal_ecx;
        static enum { not_parsed, no_mask, set_mask } status;
        unsigned int eax, ebx, ecx, edx;
@@ -233,18 +234,29 @@ static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
 
  setmask:
        /* AMD processors prior to family 10h required a 32-bit password */
-       if (c->x86 >= 0x10) {
-               wrmsr(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx);
-               wrmsr(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx);
-               if (!skip_l7s0_eax_ebx)
-                       wrmsr(MSR_AMD_L7S0_FEATURE_MASK, l7s0_ebx, l7s0_eax);
-               if (!skip_thermal_ecx) {
-                       rdmsr(MSR_AMD_THRM_FEATURE_MASK, eax, edx);
-                       wrmsr(MSR_AMD_THRM_FEATURE_MASK, thermal_ecx, edx);
-               }
-       } else {
-               wrmsr_amd(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx);
-               wrmsr_amd(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx);
+       if (!skip_feat &&
+           wrmsr_amd_safe(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx)) {
+               skip_feat = 1;
+               printk("Failed to set CPUID feature mask\n");
+       }
+
+       if (!skip_extfeat &&
+           wrmsr_amd_safe(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx)) {
+               skip_extfeat = 1;
+               printk("Failed to set CPUID extended feature mask\n");
+       }
+
+       if (!skip_l7s0_eax_ebx &&
+           wrmsr_amd_safe(MSR_AMD_L7S0_FEATURE_MASK, l7s0_ebx, l7s0_eax)) {
+               skip_l7s0_eax_ebx = 1;
+               printk("Failed to set CPUID leaf 7 subleaf 0 feature mask\n");
+       }
+
+       if (!skip_thermal_ecx &&
+           (rdmsr_amd_safe(MSR_AMD_THRM_FEATURE_MASK, &eax, &edx) ||
+            wrmsr_amd_safe(MSR_AMD_THRM_FEATURE_MASK, thermal_ecx, edx))){
+               skip_thermal_ecx = 1;
+               printk("Failed to set CPUID thermal/power feature mask\n");
        }
 }