x86/amd: Eliminate cache flushing when entering C3 on select AMD processors

AMD Fam15h processors have a shared cache. It does not need=20
to be be flushed when entering C3 and doing so causes reduces
performance. Modify acpi_processor_power_init_bm_check to
prevent these processors from flushing when entering C3.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 23e8d3991ef7fb7592a2d02fe7b2927978215778..9a416c7b2d44ec0ac164668d8e03f0e4dd7ab366 100644 (file)
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -673,7 +673,8 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag
     flags->bm_check = 0;
     if ( num_online_cpus() == 1 )
         flags->bm_check = 1;
-    else if ( c->x86_vendor == X86_VENDOR_INTEL )
+    else if ( (c->x86_vendor == X86_VENDOR_INTEL) ||
+              ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) )
     {
         /*
          * Today all MP CPUs that support C3 share cache.