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(parent: 68a8aa5) | patch
x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly
authorAndrew Cooper <andrew.cooper3@citrix.com>
Tue, 22 Sep 2020 13:46:21 +0000 (15:46 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 22 Sep 2020 13:46:21 +0000 (15:46 +0200)
commite71301ecd50f2d3bd1b960bbf7dcf850d02e7e8a
tree29c733c398aecaff900a22b6e34775372a64bbe0tree | snapshot
parent68a8aa5d7264dcb04b2c56fad24bdd5192fe5394commit | diff
x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly

This MSR doesn't exist on AMD hardware, and switching away from the safe
functions in the common MSR path was an erroneous change.

Partially revert the change.

This is XSA-333.

Fixes: 4fdc932b3cc ("x86/Intel: drop another 32-bit leftover")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Wei Liu <wl@xen.org>
xen/arch/x86/pv/emul-priv-op.c diff | blob | history
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