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(parent: 5f569f1) | patch
AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode
authorJan Beulich <jbeulich@suse.com>
Wed, 31 Jul 2019 11:23:02 +0000 (13:23 +0200)
committerJan Beulich <jbeulich@suse.com>
Wed, 31 Jul 2019 11:23:02 +0000 (13:23 +0200)
commitd9e49d1afe2ec45754734845f5c0fbc7effdd3d8
tree6a192af3c5dc51e25acfc077a38b5e2c52f6a8d3tree | snapshot
parent5f569f1ac50eff9dc95ac2e4a617de657d254b52commit | diff
AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode

In order to be able to express all possible destinations we need to make
use of this non-MSI-capability based mechanism. The new IRQ controller
structure can re-use certain MSI functions, though.

For now general and PPR interrupts still share a single vector, IRQ, and
hence handler.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Brian Woods <brian.woods@amd.com>
xen/drivers/passthrough/amd/iommu_init.c diff | blob | history
xen/include/asm-x86/hvm/svm/amd-iommu-defs.h diff | blob | history
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