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(parent: a0e1af5) | patch
x86/mce: add Xeon Icelake to list of CPUs that support PPIN
authorTony Luck <tony.luck@intel.com>
Mon, 2 Mar 2020 14:40:09 +0000 (15:40 +0100)
committerJan Beulich <jbeulich@suse.com>
Mon, 2 Mar 2020 14:40:09 +0000 (15:40 +0100)
commitcb4684e34602810c93c1e88adfd51d0e17177a99
tree70a8108c041fe71062ba7595004e9f96edcd8fb9tree | snapshot
parenta0e1af54ce7492fb267daa46120fc18f814ad4d1commit | diff
x86/mce: add Xeon Icelake to list of CPUs that support PPIN

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
[Linux commit dc6b025de95bcd22ff37c4fabb022ec8a027abf1]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/cpu/mcheck/mce_intel.c diff | blob | history
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