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(parent: 87ca6a2) | patch
x86/traps: Add Hygon Dhyana support
authorPu Wen <puwen@hygon.cn>
Thu, 4 Apr 2019 13:47:54 +0000 (21:47 +0800)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 6 Jun 2019 14:28:21 +0000 (15:28 +0100)
commitc6d427a617b3c5fd7ad716dc24e1352f7ffe024e
tree1e9e3775a5546697e73423374f3077797f10fbf9tree | snapshot
parent87ca6a2a3b4d568f6e95f38db3d9702d1c876d23commit | diff
x86/traps: Add Hygon Dhyana support

The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR0000_01DD. So add support for it if the boot param
ler is true.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/traps.c diff | blob | history
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