[PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s
authorthomas.perrot@bootlin.com <thomas.perrot@bootlin.com>
Thu, 22 Feb 2024 14:52:03 +0000 (15:52 +0100)
committerVagrant Cascadian <vagrant@debian.org>
Thu, 9 Jan 2025 19:14:04 +0000 (11:14 -0800)
commitc05b1cb8a237aa37fc2afd404c458a8452e6f836
tree0c8b43d2fbbe3f016a593925749c16806f6e5955
parent58fba3deaba48c175c71e286411e46805d19600b
[PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s

To: u-boot@lists.denx.de
Cc: Thomas Perrot <thomas.perrot@bootlin.com>
Message-ID: <20240222145203.2659671-1-thomas.perrot@bootlin.com>
Origin: https://patchwork.ozlabs.org/project/uboot/patch/20240222145203.2659671-1-thomas.perrot@bootlin.com/

It appears that there is some timing marginality either in the
board layout or the SoC that results in occasional data corruption
on some boards.
We observed this issue on some of the new HiFive Unmatched RevB
boards during volume production as well as some of the original
HiFive Unmatched boards from 2021 in our possession. This means
that there are other boards out there that might have the issue
too.

We have done some limited testing with DDR4 at 1600MT/s and
faulty boards (failing at 1866MT/s) passed.
We plan further testing after we procure a temperature chamber.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Gbp-Pq: Topic riscv64
Gbp-Pq: Name riscv-sifive-fu740-reduce-DDR-speed-from-1866MT-s-to-1600MT-s.patch
arch/riscv/dts/fu740-c000-u-boot.dtsi