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x86/pv: Add Hygon Dhyana support to emulate MSRs access
authorPu Wen <puwen@hygon.cn>
Wed, 12 Jun 2019 12:54:25 +0000 (20:54 +0800)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Wed, 12 Jun 2019 12:59:08 +0000 (13:59 +0100)
commitbbac4facb676248703cf5708001dcd40c0780add
tree32022ffae0eb36dcef16a63b81e08774c20eb6b5tree | snapshot
parentbe9e6ddfc1592086d621922fa948f8c37c3ab319commit | diff
x86/pv: Add Hygon Dhyana support to emulate MSRs access

The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
counter MSRs, hardware configuration MSR, MMIO configuration base address
MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
PV emulation infrastructure by using the code path of AMD.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/pv/emul-priv-op.c diff | blob | history
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