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(parent: fc44a70) | patch
x86/idle: prevent entering C3/C6 on some Intel CPUs due to errata
authorRoger Pau Monné <roger.pau@citrix.com>
Fri, 22 May 2020 14:08:54 +0000 (16:08 +0200)
committerJan Beulich <jbeulich@suse.com>
Fri, 22 May 2020 14:08:54 +0000 (16:08 +0200)
commitb2d502466547e6782ccadd501b8ef1482c391f2c
tree999accf3c126835c2d4a0d6644d7ba8d154ba917tree | snapshot
parentfc44a7014cafe28b8c53eeaf6ac2a71f5bc8b815commit | diff
x86/idle: prevent entering C3/C6 on some Intel CPUs due to errata

Apply a workaround for errata BA80, AAK120, AAM108, AAO67, BD59,
AAY54: Rapid Core C3/C6 Transition May Cause Unpredictable System
Behavior.

Limit maximum C state to C1 when SMT is enabled on the affected CPUs.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/cpu/intel.c diff | blob | history
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