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(parent: 28855eb) | patch
x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly
authorAndrew Cooper <andrew.cooper3@citrix.com>
Tue, 22 Sep 2020 14:09:36 +0000 (16:09 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 22 Sep 2020 14:09:36 +0000 (16:09 +0200)
commitb04d6731eedd639e078e0f0d8147c6b156875ac3
treed8ef5fd8fe0dc8f49b8c3bae9e57a6869833937ctree | snapshot
parent28855ebcdbfa437e60bc16c761405476fe16bc39commit | diff
x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly

This MSR doesn't exist on AMD hardware, and switching away from the safe
functions in the common MSR path was an erroneous change.

Partially revert the change.

This is XSA-333.

Fixes: 4fdc932b3cc ("x86/Intel: drop another 32-bit leftover")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Wei Liu <wl@xen.org>
xen/arch/x86/pv/emul-priv-op.c diff | blob | history
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