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(parent: c5004d3) | patch
x86/EPT: fix pinned cache attribute range checking
authorJan Beulich <jbeulich@suse.com>
Fri, 2 May 2014 08:50:55 +0000 (10:50 +0200)
committerJan Beulich <jbeulich@suse.com>
Fri, 2 May 2014 08:50:55 +0000 (10:50 +0200)
commitaaef67041b6974800ab8f421900559db14bb5903
treef982a87e61231d8d9163f22a4657d7a5c90f8211tree | snapshot
parentc5004d34693341e2b368467fad1860e53cb5a5d8commit | diff
x86/EPT: fix pinned cache attribute range checking

This wasn't done properly by 4d66f069 ("x86: fix pinned cache attribute
handling"): The passed in GFN shouldn't be assumed to be order aligned.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Tim Deegan <tim@xen.org>
xen/arch/x86/hvm/mtrr.c diff | blob | history
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