x86/ucode/intel: Fix handling of microcode revision
authorAndrew Cooper <andrew.cooper3@citrix.com>
Mon, 26 Oct 2020 15:27:35 +0000 (15:27 +0000)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Wed, 27 Jan 2021 20:29:43 +0000 (20:29 +0000)
commitaa1b136ff1798a2c1a81270ccd20e7252e30ff1f
treec82dfdd4550e0ff6a33ccca20bbba00d78ed77c6
parent754865c298174560c9724bfcb2c1abb6fbc118ac
x86/ucode/intel: Fix handling of microcode revision

For Intel microcode blobs, the revision field is signed (as documented in the
SDM) and negative revisions are used for pre-production/test microcode (not
documented publicly anywhere I can spot).

Adjust the revision checking to match the algorithm presented here:

  https://software.intel.com/security-software-guidance/best-practices/microcode-update-guidance

This treats pre-production microcode as always applicable, but also production
microcode having higher precedent than pre-production.  It is expected that
anyone using pre-production microcode knows what they are doing.

This is necessary to load production microcode on an SDP with pre-production
microcode embedded in firmware.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/cpu/microcode/intel.c