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(parent: 009360a) | patch
x86/cpuidle: correct Cannon Lake residency MSRs
authorJan Beulich <jbeulich@suse.com>
Fri, 3 Apr 2020 15:15:58 +0000 (17:15 +0200)
committerJan Beulich <jbeulich@suse.com>
Fri, 3 Apr 2020 15:15:58 +0000 (17:15 +0200)
commit9ff09aefc46385dc04c38b6dd1f1ac25f784f482
tree1c250dcda0053d488b0db4abcaf12b4023db72d7tree | snapshot
parent009360acc9c90513e4a85c7285d4fd7a665c66e1commit | diff
x86/cpuidle: correct Cannon Lake residency MSRs

As per SDM rev 071 Cannon Lake has
- no CC3 residency MSR at 3FC,
- a CC1 residency MSR ar 660 (like various Atoms),
- a useless (always zero) CC3 residency MSR at 662.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/acpi/cpu_idle.c diff | blob | history
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