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(parent: ed00f17) | patch
x86emul: honor MXCSR.MM
authorJan Beulich <jbeulich@suse.com>
Fri, 14 Oct 2016 12:08:29 +0000 (14:08 +0200)
committerJan Beulich <jbeulich@suse.com>
Fri, 14 Oct 2016 12:08:29 +0000 (14:08 +0200)
commit9d3118a4d5a6fbd9f578853ec81621501caad63d
tree742a252231e75a3fb5c26f903a257cd2252be597tree | snapshot
parented00f1761689ac7b9c074e9084c81e47c25d460ccommit | diff
x86emul: honor MXCSR.MM

Commit 6dc9ac9f52 ("x86emul: check alignment of SSE and AVX memory
operands") didn't consider a specific AMD mode: Mis-alignment #GP
faults can be masked on some of their hardware.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/x86_emulate/x86_emulate.c diff | blob | history
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