tools/pvh: set coherent MTRR state for all vCPUs
authorRoger Pau Monne <roger.pau@citrix.com>
Wed, 10 Oct 2018 14:39:35 +0000 (16:39 +0200)
committerWei Liu <wei.liu2@citrix.com>
Thu, 11 Oct 2018 08:42:38 +0000 (09:42 +0100)
commit92666fdd6e0afab989b2d89759d9b43f2c645ae7
tree1e1b0337625d0c11f335ed354b1ea264023bae16
parent23058e7b361a4f6cf740245327ea1841e2be9132
tools/pvh: set coherent MTRR state for all vCPUs

Instead of just doing it for the BSP. This requires storing the
maximum number of possible vCPUs in xc_dom_image.

This has been a latent bug so far because PVH doesn't yet support
pci-passthrough, so the effective memory cache attribute is forced to
WB by the hypervisor. Note also that even without this in place vCPU#0
is preferred in certain scenarios in order to calculate the memory
cache attributes.

Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
tools/libxc/include/xc_dom.h
tools/libxc/xc_dom_x86.c
tools/libxl/libxl_dom.c