x86/msr: Handle MSR_AMD64_DR{0-3}_ADDRESS_MASK in the new MSR infrastructure

x86/msr: Handle MSR_AMD64_DR{0-3}_ADDRESS_MASK in the new MSR infrastructure

This is a followup to c/s 96f235c26 which fulfils the remaining TODO item.

First of all, the pre-existing SVM code has a bug.  The value in
msrs->dr_mask[] may be stale, as we allow direct access to these MSRs.
Resolve this in guest_rdmsr() by reading directly from hardware in the
affected case.

With the reading/writing logic moved to the common guest_{rd,wr}msr()
infrastructure, the migration logic can be simplified.  The PV migration logic
drops all of its special casing, and SVM's entire {init,save,load}_msr()
infrastructure becomes unnecessary.

The resulting diffstat shows quite how expensive the PV special cases where in
arch_do_domctl().

  add/remove: 0/3 grow/shrink: 4/6 up/down: 465/-1494 (-1029)
  Function                                     old     new   delta
  guest_rdmsr                                  252     484    +232
  guest_wrmsr                                  653     822    +169
  msrs_to_send                                   8      48     +40
  hvm_load_cpu_msrs                            489     513     +24
  svm_init_msr                                  21       -     -21
  hvm_save_cpu_msrs                            365     343     -22
  read_msr                                    1089    1001     -88
  write_msr                                   1829    1689    -140
  svm_msr_read_intercept                      1124     970    -154
  svm_load_msr                                 195       -    -195
  svm_save_msr                                 196       -    -196
  svm_msr_write_intercept                     1461    1265    -196
  arch_do_domctl                              9581    9099    -482
  Total: Before=3314610, After=3313581, chg -0.03%

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by:  Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>