x86/setup: Rework MSR_S_CET handling for CET-IBT
authorAndrew Cooper <andrew.cooper3@citrix.com>
Mon, 1 Nov 2021 16:13:29 +0000 (16:13 +0000)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Fri, 25 Mar 2022 17:06:38 +0000 (17:06 +0000)
commit86a98948b9f8236de30651e5588f592bc5468da2
tree74c4a6c23626b603c4d0457844464871bc8cc799
parent9cd9650377d564f56126b2974097f54e0318dd27
x86/setup: Rework MSR_S_CET handling for CET-IBT

CET-SS and CET-IBT can be independently controlled, so the configuration of
MSR_S_CET can't be constant any more.

Introduce xen_msr_s_cet_value(), mostly because I don't fancy
writing/maintaining that logic in assembly.  Use this in the 3 paths which
alter MSR_S_CET when both features are potentially active.

To active CET-IBT, we only need CR4.CET and MSR_S_CET.ENDBR_EN.  This is
common with the CET-SS setup, so reorder the operations to set up CR4 and
MSR_S_CET for any nonzero result from xen_msr_s_cet_value(), and set up
MSR_PL0_SSP and SSP if SHSTK_EN was also set.

Adjust the crash path to disable CET-IBT too.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
(cherry picked from commit 311434bfc9d10615adbd340d7fb08c05cd14f4c7)
xen/arch/x86/acpi/wakeup_prot.S
xen/arch/x86/boot/x86_64.S
xen/arch/x86/crash.c
xen/arch/x86/setup.c
xen/include/asm-x86/msr-index.h