x86/splitlock: CPUID and MSR details

x86/splitlock: CPUID and MSR details

A splitlock is an atomic operation which crosses a cache line boundary.  It
serialises operations in the cache coherency fabric and comes with a
multi-thousand cycle stall.

Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various core-specific
features, and MSR_TEST_CTRL to adjust the behaviour in the case of a
splitlock.

Virtualising this for guests is distinctly tricky owing to the fact that
MSR_TEST_CTRL has core rather than thread scope.  In the meantime however,
prevent the MSR values leaking into guests.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>