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(parent: 8f81064) | patch
xen/arm: Add CP10 exception support to handle MVFR
authorBertrand Marquis <bertrand.marquis@arm.com>
Thu, 17 Dec 2020 15:38:07 +0000 (15:38 +0000)
committerStefano Stabellini <sstabellini@kernel.org>
Mon, 4 Jan 2021 19:27:21 +0000 (11:27 -0800)
commit73ff36144014218f796f7e07c1224a1c580012d1
tree1d1f097e2d9c9f4615de9eddc534463e2ca710e7tree | snapshot
parent8f81064a07c64952931eafdd9a9a3017ed6ffd26commit | diff
xen/arm: Add CP10 exception support to handle MVFR

Add support for cp10 exceptions decoding to be able to emulate the
values for MVFR0, MVFR1 and MVFR2 when TID3 bit of HSR is activated.
This is required for aarch32 guests accessing MVFR registers using
vmrs and vmsr instructions.

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
xen/arch/arm/traps.c diff | blob | history
xen/arch/arm/vcpreg.c diff | blob | history
xen/include/asm-arm/perfc_defn.h diff | blob | history
xen/include/asm-arm/traps.h diff | blob | history
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