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Intel/VPMU: Add support for full-width PMC writes
authorBoris Ostrovsky <boris.ostrovsky@oracle.com>
Wed, 7 Aug 2013 07:51:02 +0000 (09:51 +0200)
committerJan Beulich <jbeulich@suse.com>
Wed, 7 Aug 2013 07:51:02 +0000 (09:51 +0200)
commit330c2e4e9430855cd7e5dd45b247ccc27bf92c7a
treef864d3856894e5e38e92b4447e3021125829a8b1tree | snapshot
parent66450c1d1ab3c4480bbba949113b95d1ab6a943acommit | diff
Intel/VPMU: Add support for full-width PMC writes

A recent Linux commit (069e0c3c405814778c7475d95b9fff5318f39834) added
support for full-width PMC writes to performance counter registers,
making these registers default for perf. Since current Xen VPMU does
not support these new MSRs perf will fail to initialise in guests.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Acked-by: Keir Faser <keir@xen.org>
xen/arch/x86/hvm/vmx/vpmu_core2.c diff | blob | history
xen/include/asm-x86/msr-index.h diff | blob | history
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