ARM: vPL011: Use the VGIC's level triggered IRQs handling if available
authorAndre Przywara <andre.przywara@linaro.org>
Mon, 18 Dec 2017 17:34:24 +0000 (17:34 +0000)
committerStefano Stabellini <sstabellini@kernel.org>
Tue, 27 Mar 2018 19:44:32 +0000 (12:44 -0700)
commit31286f7a38d65ee461f88282ffacb1de00238a49
tree140739479f67d183a7ec9bf0d959889194b040e5
parent885aff8e42efbb6a290919efb194509429b3a9e7
ARM: vPL011: Use the VGIC's level triggered IRQs handling if available

The emulated ARM SBSA UART is using level triggered IRQ semantics,
however the current VGIC can only handle edge triggered IRQs, really.
Disable the existing workaround for this problem in case we have the
new VGIC in place, which can properly handle level triggered IRQs.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
xen/arch/arm/vpl011.c