x86/ept: defer enabling of EPT A/D bit until PML get enabled
authorKai Huang <kai.huang@linux.intel.com>
Wed, 21 Oct 2015 08:49:16 +0000 (10:49 +0200)
committerJan Beulich <jbeulich@suse.com>
Wed, 21 Oct 2015 08:49:16 +0000 (10:49 +0200)
commit2ed8b8363269554a3b91e99b3acdecac52f8b500
tree6d33b1d29f1f346388936c433b4dbc4f07cc2da6
parenta5e6c75bb0da85b2021c80d7b27bef77a00c1da2
x86/ept: defer enabling of EPT A/D bit until PML get enabled

Existing PML implementation turns on EPT A/D bit unconditionally if PML is
supported by hardware. This works but enabling of EPT A/D bit can be deferred
until PML get enabled. There's no point in enabling the extra feature for every
domain when we're not meaning to use it (yet).

Also added ASSERT of domain having been paused to ept_flush_pml_buffers to make
it consistent with ept_enable{disable}_pml.

Sanity live migration and GUI display were tested on Broadwell Machine.

Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
xen/arch/x86/hvm/vmx/vmcs.c
xen/arch/x86/mm/p2m-ept.c
xen/include/asm-x86/hvm/vmx/vmcs.h