x86/spec-ctrl: Mitigations for LazyFPU
authorAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 7 Jun 2018 16:00:37 +0000 (17:00 +0100)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Wed, 13 Jun 2018 20:45:17 +0000 (21:45 +0100)
commit243435bf67e8159495194f623b9e4d8c90140384
tree7a197cf18144ed70d8839dceb176b254d387a5fe
parent146dfe9277c2b4a8c399b229e00d819065e3167b
x86/spec-ctrl: Mitigations for LazyFPU

Intel Core processors since at least Nehalem speculate past #NM, which is the
mechanism by which lazy FPU context switching is implemented.

On affected processors, Xen must use fully eager FPU context switching to
prevent guests from being able to read FPU state (SSE/AVX/etc) from previously
scheduled vcpus.

This is part of XSA-267 / CVE-2018-3665

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
docs/misc/xen-command-line.markdown
xen/arch/x86/i387.c
xen/arch/x86/spec_ctrl.c
xen/include/asm-x86/spec_ctrl.h