ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK

ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK

The board uses T-topology for the four x16 DRAM chips, so remove
the write-leveling from the SPL as that is only usefly on fly-by
topology and can be harmful on T-topology. Also update the DRAM
timing with values from calibration on multiple boards.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Gbp-Pq: Topic upstream
Gbp-Pq: Name 0001-ARM-imx6-Adjust-DDR-DRAM-settings-on-DHCOM-i.MX6-PDK.patch