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(parent: b6ecd5c) | patch
x86/AMD: also determine L3 cache size
authorJan Beulich <jbeulich@suse.com>
Mon, 17 May 2021 13:40:53 +0000 (15:40 +0200)
committerJan Beulich <jbeulich@suse.com>
Mon, 17 May 2021 13:40:53 +0000 (15:40 +0200)
commit12a963b22b02a377ddb6a46db304fa4a0eee8c39
tree7d94881bd970c220deeb1aa8582ea0f26fd09d86tree | snapshot
parentb6ecd5c8bc0b9727f095c0bb2fedf62a565417f1commit | diff
x86/AMD: also determine L3 cache size

For Intel CPUs we record L3 cache size, hence we should also do so for
AMD and alike.

While making these additions, also make sure (throughout the function)
that we don't needlessly overwrite prior values when the new value to be
stored is zero.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/cpu/common.c diff | blob | history
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