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(parent: 9a67ffe) | patch
x86/amd: Work around CLFLUSH ordering on older parts
authorAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 9 Jun 2022 12:23:07 +0000 (14:23 +0200)
committerJan Beulich <jbeulich@suse.com>
Thu, 9 Jun 2022 12:23:07 +0000 (14:23 +0200)
commit062868a5a8b428b85db589fa9a6d6e43969ffeb9
tree16a74923b3f339f1f474c1f12442140e7cd882e3tree | snapshot
parent9a67ffee3371506e1cbfdfff5b90658d4828f6a2commit | diff
x86/amd: Work around CLFLUSH ordering on older parts

On pre-CLFLUSHOPT AMD CPUs, CLFLUSH is weakely ordered with everything,
including reads and writes to the address, and LFENCE/SFENCE instructions.

This creates a multitude of problematic corner cases, laid out in the manual.
Arrange to use MFENCE on both sides of the CLFLUSH to force proper ordering.

This is part of XSA-402.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/cpu/amd.c diff | blob | history
xen/arch/x86/flushtlb.c diff | blob | history
xen/arch/x86/include/asm/cpufeatures.h diff | blob | history
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