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(parent: 10f0b2d) | patch
x86/Intel: insert Tiger Lake model numbers
authorJan Beulich <jbeulich@suse.com>
Fri, 4 Jun 2021 12:51:25 +0000 (14:51 +0200)
committerJan Beulich <jbeulich@suse.com>
Fri, 4 Jun 2021 12:51:25 +0000 (14:51 +0200)
commit02f9760498ce1c4fb320045f3f3b8f515d124ad4
tree6917fa3ebdc07dd623c88279d94e428819bf828dtree | snapshot
parent10f0b2d49376865d49680f06c52b451fabce3bb5commit | diff
x86/Intel: insert Tiger Lake model numbers

Both match prior generation processors as far as LBR and C-state MSRs
go (SDM rev 073). The if_pschange_mc erratum, according to the spec
update, is not applicable.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
master commit: e93c3712d67098453760fd61c338cbf62dd08da1
master date: 2020-12-22 09:00:03 +0100
xen/arch/x86/acpi/cpu_idle.c diff | blob | history
xen/arch/x86/hvm/vmx/vmx.c diff | blob | history
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